Senior Staff Physical Design and Integration Lead
Company: Marvell Semiconductor, Inc.
Location: Santa Clara
Posted on: May 3, 2024
Job Description:
About Marvell Marvell's semiconductor solutions are the
essential building blocks of the data infrastructure that connects
our world. Across enterprise, cloud and AI, automotive, and carrier
architectures, our innovative technology is enabling new
possibilities.At Marvell, you can affect the arc of individual
lives, lift the trajectory of entire industries, and fuel the
transformative potential of tomorrow. For those looking to make
their mark on purposeful and enduring innovation, above and beyond
fleeting trends, Marvell is a place to thrive, learn, and lead.Your
Team, Your ImpactThe Compute Custom and Storage (CCS) team at
Marvell is seeking candidates for a Senior Staff Physical Design
and Integration Lead engineering position. Projects within CCS
range from artificial intelligence and machine learning, to wired
and wireless infrastructure, with the latest technology nodes. The
team utilizes the latest EDA software tools, and work through the
technical challenges to insure we meet the performance, power, and
area requirements of the design. This position will work in tandem
with the other Physical Design related teams, such as Timing,
Physical Verification, Power Integrity and other teams both at a
local and global level.What You Can Expect
- In this hybrid role at a CCS site, you will be the leader on a
large complex sub-system/partition through all phases of the
design
- Responsible for floorplanning a sub-system/partition, pushing
down block boundary and pin assignment to team members
- Work with a variety of teams to pull in their required portion
of the sub-system, such as DFT and clock distribution teams
- Leading a small group of engineers at the block level, insuring
they are progressing, meeting milestones on schedule and quality,
and correct deliverables
- Work closely with the block level PD engineers in debugging and
resolving timing and routing issues across all hierarchical levels
- Be an active team member on physical design methodology and
flow development
- Provide technical direction, coaching, and mentoring to
employees on your team and others when necessary to achieve
successful project outcomes
- Write scripts in Perl, Python and TCL to extract data and
achieve productivity enhancements through automationWhat We're
Looking For
- Bachelor's degree in Computer Science, Electrical Engineering
or related fields and 5-10 years of related professional
experience. OR Master's degree and/or PhD in Computer Science,
Electrical Engineering or related fields with 3-5 years of
experience.
- 3 years practical experience in physical design at all levels
of hierarchy with multiple ASICs/SOCs
- Physical design knowledge and experience, from netlist handoff
to GDS tape-out
- Extensive experience with floorplanning at a
sub-system/partition level, considering boundary snap of
power/technology and pin assignment
- Proficient in running sub-system/partition level signoff,
including physical verification (DRC and LVS), along with power
integrity (EMIR)
- Experienced leading a small team of block level engineers,
coordinating at the sub-system/partition level
- Good knowledge of Verilog/VHDL, and track record of
collaboration with RTL team
- Good understanding of digital logic and architecture
- Proficient in UNIX, and shell based scripting
- Knowledge and experience with TCL language
- Diligent, detail-oriented, and able to handle assignments with
minimal supervision
- Must possess good communication skills, be a self-driven
individual and a good team playerPreferred Qualifications (in
addition to the minimum qualifications)
- 5 years practical experience as a leader of a small team at the
sub-system/partition level for multiple ASICs/SOCs
- Worked with timing and clock teams on planning and integration
of high speed clock distribution
- 5nm/3nm experience with floor planning
- Floorplanning and Physical Design with Cadence Innovus
- Physical Verification with Siemens Calibre
- Power Integrity Signoff with Cadence Voltus
- Peripheral IO Pad assignment and associated RDL
- Bump assignment planning and collaboration with fullchip and
package team
- Experience with Analog IP integration and implementation
- Knowledge and experience with Python language
- Experience with low power design methodology and
implementation
- Have led or participated in Physical Design and Integration
methodology and flow development#LI-TM1Expected Base Pay Range
(USD)123,200 - 182,370, $ per annumThe successful candidate's
starting base pay will be determined based on job-related skills,
experience, qualifications, work location and market conditions.
The expected base pay range for this role may be modified based on
market conditions.Additional Compensation and Benefit ElementsAt
Marvell, we offer a total compensation package with a base, bonus
and equity.Health and financial wellbeing are part of the package.
That means flexible time off, 401k, plus a year-end shutdown,
floating holidays, paid time off to volunteer. Have a question
about our benefits packages - health or financial? Ask your
recruiter during the interview process.This role is eligible for
our hybrid work model in which you will be able to split time
between working from home and on-site in a Marvell office.All
qualified applicants will receive consideration for employment
without regard to race, color, religion, sex, national origin,
sexual orientation, gender identity, disability or protected
veteran status.Any applicant who requires a reasonable
accommodation during the selection process should contact Marvell
HR Helpdesk at TAOps@marvell.com.
Keywords: Marvell Semiconductor, Inc., Milpitas , Senior Staff Physical Design and Integration Lead, Other , Santa Clara, California
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